1. Field of Disclosure
The present invention relates to the design of memory systems and more specifically to write leveling of the memory units employed in such memory systems.
2. Related Art
There are several memory systems in which memory units are designed to receive access requests in a sequential chained topology. In such systems, a memory controller typically sends control and address information on a single path, which passes the information to each of the memory units sequentially in the same order as in which the memory units are chained. DDR3 technology based memory systems are examples of such memory systems, with DRAMs being used as memory units, as is well known in the relevant arts.
Write leveling is often performed prior to performing write operations in such memory systems. Write leveling generally entails determining delays with which different signals need to be asserted during write operations, given the various delays that could occur in the sequential chained topology.
For example, in the case of DDR3 based technologies, it may be desirable to assert a strobe signal synchronous with (at the same time instance) a rising edge of the clock signal received from the memory controller on the single path. However, at least due to the fly-by delay in the single path, different memory units may receive the rising edge with different delays. It may therefore be necessary to determine the specific corresponding delay with which the strobe signal is to be asserted for each of the memory units
Once such delays are determined, the various signals can be asserted with appropriate timing for a desired level of throughput performance and accuracy during write operations.
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